In electronics manufacturing, integrated circuit packaging refers to encapsulating an integrated circuit formed on a semiconductor die into a package device, such as a case, housing, or the like. The package device can help protect the semiconductor die from its environment, for example, from physical damage, corrosion, or the like. The package device also can include an interconnect to electrically connect interface pins of the semiconductor die to leads or solder bumps of the package device.
As complexity of integrated circuits grows, so too has the complexity of package devices. For example, some package devices may be designed to accommodate multiple semiconductor dies, each including thousands of pads, pins, or solder bumps to be supported by the interconnect in the package device. These package devices can include many stacked layers with traces to route connections on a layer and vias to provide inter-layer electrical connectivity.
Package device design is often performed concurrently with design and/or testing of the integrated circuit(s). While this concurrent design of the integrated circuit(s) and a corresponding package device can speed up development time, alterations in a design of the integrated circuit(s) can prompt re-design in the package design. For example, a manufacturer can perform environmental testing on a physical layout design of an integrated circuit to estimate manufacturing yield and/or reliability of a manufactured integrated circuit. Based the results of this testing, the physical layout design can be modified, for example, slightly shifting pins of the integrated circuit to new locations in an attempt to improve yield or reliability. In some examples, this modification of the physical design layout can cause designers to manually modify the package design with a design tool, for example, a user manually provides input to the design tool to re-align traces or vias in the package design, to re-assign net names to routes in the package design, or the like.